The present invention relates to a system of supporting designing of a computer system and, particularly, relates to a design support system adapted for use in work management in a process of logic verification of computer system design data and a process following the first-mentioned process.
Logic verification is generally one important process in development of a computer system. Before a prototype machine is produced really, sufficient logic verification is performed to secure logic quality, so that verification on the prototype machine can be performed in a short time to reduce the number of times of redesigning of the prototype machine to thereby reduce both the time and cost required for the development. As one of means for supporting the logic verification, logic simulation is known. It is however not possible to perform perfect logic verification only by using logic simulation. Accordingly, also manual, desk verification becomes essential.
The aforementioned logic verification is generally carried out by the following method.
First of all, a specification for verification is generated on the basis of a specification for design of logic which is a subject of logic verification. This specification for verification provides the outline of verification content and method. Then, verification items are generated on the basis of the specification of these verification content and method. In the generation of verification items, verification means to be used such as logic simulation, manual checking, etc. are determined for every verification item and, at the same time, the date scheduled to be digested is determined for every verification item. Generally, verification is started from a basic function and other functions are verified gradually successively. Then, a logic simulation environment is constructed on the basis of the specification for verification. Then, the verification items are digested by logic simulation and desk verification manually.
In the case where logic simulation is used for verification, first, test data and an expected value thereof are generated in accordance with each of the verification items. Logic simulation is executed by using the test data, and the result of the simulation is compared with the expected value to thereby determine success/failure. If the result as has been expected is obtained, the verification item is considered to be already digested. Otherwise, a measure obtained by logic analysis is applied and then verification on the item in question is executed again.
The afore-mentioned method is a general logic verification method. However, there arises a problem that not only logic verification means and accuracy but also management in progress of a process and quality of logic becomes difficult as the logic scale of the computer system increases.
That is, since the larger the number of items to be verified becomes the larger the logic scale becomes, it is necessary that a project team is constituted by a large number of members so that logic verification is performed by the large number of members. Assume now that, for example, all the members or managers are classified into verification managers and logic correction managers, and that the verification managers are further classified into desk verification managers and logic simulation managers. At this time, in accordance with the logic scale to be handled, there is a case where even the required number of the logic simulation managers becomes from the order of several persons to the order of tens of persons.
In the logic verification executed by such a project team, management of the state of digestion of verification items and management of the state of extraction of failures and measure thereof become important. If these managements are insufficient, the state of progress becomes worse so that the state of production of failures cannot be grasped accurately. Accordingly, there is a risk that it becomes difficult to secure logic quality in an early stage. Further, the logical problem which arises currently cannot be transmitted to the whole project team, so that returns inward may be caused by execution of wasteful logic simulation and the like. Accordingly, there is a risk that the throughput in the computer resources as well as in the man-hour becomes worse.
As a conventional technique for supporting such management of logic verification as mentioned above, for example, a failure measure management system described in JP-A-4-188333 is known.
In this technique, a logic verification manager registers failure information on a table in the failure management system whenever a logic failure is extracted through logic simulation or the like. Totalization and display of failure information is performed by the system. By using the information, a verification process manager manages logic quality and the state of progress of verification.
Generally, when a failure is extracted in verification of a certain item, verifying work such as logic simulation, etc. with respect to the verification item from which the failure is extracted must be interrupted unless the measure counter to the failure is completed and, in addition, verifying work with respect to other verification items scheduled to be executed after the confirmation of the item must be interrupted.
(1) The conventional technique cannot be adapted for handling the aforementioned management. Accordingly, the management must be carried out manually by the verification manager. Because the number of verification items to be handled increases as the project scale becomes large, a great deal of time and labor is required for the management. PA0 (2) Further, in the conventional technique, the state of extracted failures must be inputted manually, so that a large load due to the man-hour required for inputting failure information for the purpose of failure management is imposed on the logic verification manager who is always driven by execution and confirmation of logic simulation. PA0 (3) Generally, after the completion of the logic verification, a process of generating packaging data to arrange parts and logic blocks to thereby determine wiring is carried out. However, when the packaging data generating process is to be carried out under the condition in which logic verification is insufficient, returns inward will be caused by the production of serious failures. Conventionally, because this management is put into human hands, a packaging process may be carried out before confirmation of completeness of the logic verification. Accordingly, there arises a problem that returning of process may be caused by failures after the packaging process.